TeraView expands its intellectual property portfolio in Korea and Taiwan protecting semiconductor chip test & inspection

TeraView is pleased to announce a newly granted US patent that covers a pioneering test system designed for devices with multiple electrical contacts, integrating a movable probe assembly and a sophisticated profile-determining system. This system ensures precise mapping and reliable testing of advanced 2.5/3D packaging used in chips for artificial intelligence (AI), machine learning as well as chips planned for other applications such as 5G and the Internet of Things (IoT). This recent patent lays the groundwork for future automation in device analysis, with its implementation realised in TeraView’s advanced EOTPR 4500 device prober instrument. The integration will empower EOTPR to deliver automated, high-accuracy, electrical characterisation, addressing the demands of next-generation IC packaging with unprecedented precision and efficiency.

The significance of this patented technology is underscored by another major purchase of TeraView’s EOTPR 4500 technology by a leading semiconductor company establishing a new assembly and test manufacturing facility for memory products in the Asia-Pacific region. The adoption of the EOTPR 4500 for this task, renowned for its world-leading sub-5 µm fault isolation and fully automated probe capabilities, highlights growing industry confidence in TeraView’s solution for advanced IC packaging challenges. This landmark customer deployment demonstrates the EOTPR 4500’s critical role in supporting the quality and efficiency demands of large-scale, next-generation memory manufacturing.

Advanced packaging is critically important in semiconductor AI chips because it allows for the integration of multiple chips into a single package, which increases performance, improves power efficiency, and reduces costs. As traditional chip scaling reaches its limits, advanced packaging techniques like 2.5D and 3D integration enable higher logic-to-logic and logic-to-memory bandwidth, which are crucial for demanding AI workloads. Advanced packaging is thus becoming a cornerstone in the scaling of AI chip production. EOTPR was originally developed by TeraView jointly with Intel to address the gap in failure analysis and inspection technologies in advanced packaging. The rapidly increasing adoption of advanced packing is thus driving the need for EOTPR in the production of chips for AI and other applications.

Dr Don Arnone, TeraView’s CEO, commented “The grant of an additional patent in the US augments recent patents granted in Korea and other geographies protecting our EOTPR platform. The patent further cements TeraView’s dominance in supplying solutions to customers in the 2.5/3D advanced packaging market. EOTPR is now being purchased for and deployed as a standard tool in customer failure analysis and quality assurance facilities at production sites. The fact that these production facilities require EOTPR demonstrates its importance to suppliers of key components for AI chips and other semiconductor devices utilising advanced packaging. The fact that AI chip providers are themselves citing the importance of our technology is key to the growth in adoption of EOTPR that we are now seeing.”