Defect Localization in Through-Si-Interposer Based 2.5D ICs
Gourikutty, Sajay Bhuvanendran Nair, Yew Meng Chow, Jesse Alton, Ratan Bhimrao Umralkar, Haonan Bai, Kok Keng Chua, and Surya Bhattacharya. “Defect localization in through-Si-interposer based 2.5 D ICS.” In 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), pp. 1180-1185. IEEE, 2020.
Advanced packaging solutions using Through Silicon Interposers (TSI) are an attractive option to create 2.5D ICs. In many applications such as GPU and FPGA, 2.5D ICs can overcome the power, performance, and form-factor limitations of traditional IC packages. Investigating yield-loss and reliability mechanisms of such packages is made particularly challenging by the multitude of possible failure locations such as in TSV, micro-bumps, underfill, solder ball joints and RDL layers. Existing electrical and physical failure analysis tools do not have adequate resolution to accurately localize the failure in 2.5D IC. In this paper, we present a non-destructive methodology to carry out the failure analysis by localizing the defects which are entirely internal to the package and inaccessible from the exterior. In a through silicon interposer based FPGA package, a short failure has been successfully located with an accuracy of less than 10μm without the need for any sample preparation. The testing, fault localization and physical failure analysis of advanced package demonstrated here will provide a cost-effective method for improving manufacturing yield.
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