Case studies of accurate fault localization in advanced packages
Gourikutty, Sajay Bhuvanendran Nair, Jesse Alton, Desmond Yeo, Kok Keng Chua, Sharon Lim Seow Huang, and Surya Bhattacharya. “Case studies of accurate fault localization in advanced packages.” In 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), pp. 850-855. IEEE, 2021.
Advanced wafer-level packaging has been successfully used in state-of-the-art FPGA ICs, smart-phone application processors, and GPU units to provide power-performance-form factor boosts that are not obtainable by conventional packaging. In addition, very fine pitch interconnects approaches such as high-density fan-out on organic substrates and fine pitch silicon interposers enable the need for heterogeneous integration and scaling demand. However, this increased the intricacy of package architecture which leads to a higher possibility of failures making it challenging to attain high yield in volume production. Therefore, high failure analysis success is required in this area and without accurate fault localization, failure analysis is difficult and often reliant on a best-guess approach which tends to be time-consuming and relatively expensive to be implemented. In this work, we demonstrated a rapid methodology for non-destructive accurate defect isolation at various levels of the advanced ICs preventing potential artifacts. First, fault isolation is verified on a 2.5D advanced package where an open fault is successfully localized after the micro-bump in the die side metal layer. Secondly, the methodology is validated by employing fine pitch interposer chip samples by isolating defects including high resistance fault in RDL metal lines.
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