NVIDIA publishes two papers to discuss their methods of deploying TeraView EOTPR systems

Feb 28, 2024

TeraView, the pioneer and leader in terahertz technology and solutions, is pleased to announce that NVIDIA has presented two papers at the semiconductor industry’s annual failure analysis conference ISTFA 2023 on the importance of TeraView’s EOTPR product for semiconductor chip-level failure analysis.

NVIDIA’s papers detailed several case studies around integrated circuit failures, and demonstrated the importance of the EOTPR product in rapidly identifying the cause of these issues in each of the case studies.

In one of the papers presented by Dr Joy Liao, NVIDIA states ‘EOTPR has been proven to be an effective non-destructive fault isolation technique for chip-level FA, especially for IO failures.’

NVIDIA also notes that ‘EOTPR is now integrated in our FI workflow as the first non-destructive technique to utilize in chip-level FA. While we continue to explore and extend its usefulness into silicon die, we are working to improve the throughput and workflow for volume FA so that we can enable EOTPR capability in OSAT/Foundry partners.’

Martin Igarashi, TeraView’s VP of Semiconductor noted ‘I would like to thank Dr Liao and Dr Zhang who presented these two papers at the conference. These publications represent NVIDIA’s confidence in deploying EOTPR technology in the failure analysis lab, and encourage their suppliers to do the same.

Dr Don Arnone, TeraView’s CEO, commented ‘This is an important milestone in the adoption of TeraView’s EOTPR product as a technology of record for use in chip-level failure analysis. Significantly, NVIDIA are using TeraView systems in conjunction with their regular test equipment and integrating EOTPR into their regular workflow. We are proud to be working in collaboration with NVIDIA and its suppliers to meet their needs in advanced semiconductor packaging.

Link to papers:

Paper 1: Incorporating Time-Domain Reflectometry in Chip-Level Failure Analysis Workflow: Case Studies
Paper 2: High-Precision Pulse Reflectometry-Based Fault Localization Approach for Advanced Chip Package Failures